1. Field
The present invention relates to a control technique of writing/erasing of a multi-dot flash memory (MDF).
2. Related Art
A NAND flash memory which has been dominating file memory market has a serious problem of performance deterioration due to repetition of the writing/erasing, because a tunnel insulating film used at the time of writing/erasing is also used as a gate insulating film which determines the transistor characteristic of a cell. Such problem in reliability of the tunnel insulating film is disclosed in Fujio Masuoka, “Flash Memory Technology Handbook”, publish on demand, released in August, 1993.
In addition, since the NAND flash memory cannot be written in at random, it is not suitable for high-speed large-volume data recording. Therefore, a large-capacity buffer memory is required to record a moving image in real time.
The well-known memory cell structures of the NAND flash memory are a floating gate type using a floating gate to retain a charge, and a local trap type using a charge accumulation layer composed of local traps highly contained in a nitride film, but whether they can be miniaturized to 30 nm or less is doubtful for the following reason.
First, the floating gate type largely used in the market at present has a serious problem of an interference effect between two adjacent floating gates (inter-cell interference), which prevents miniaturization.
This inter-cell interference is disclosed in Andrea Ghetti, Luca Bortesi and Loris Vendrame, “3D Simulation study of gate coupling and gate cross-interference in advanced floating gate non-volatile memories”, Solid-State Electronics, vol. 49, Issue 11, November 2005, Pages 1805-1812, for example.
As the quickest method to solve the above problem, both a tunnel insulating film provided between a channel and a floating gate and an inter-electrode insulating film (IPD (Inter-Polysilicon Dielectric), for example) provided between the floating gate and a control gate are thinned, and lateral shrinkage and vertical shrinkage are implemented at the same time.
Although this method is subject to a scaling law (refer to R. H. Dennard et al., “Design of ion-implanted MOSFET's with very small physical dimensions”, IEEE j. of SSC, vol. 9, no. 5, pp. 256-268, 1974, for example) and the most effective method, the writing/erasing have to be performed using the tunnel insulating film. As a result, a charge trap is generated on the side of the floating gate at the time of writing, and the charge trap is generated on the side of the substrate at the time of erasing.
Therefore, as for the memory cell, a difference (threshold window) between a threshold value in a write state and a threshold value in an erase state becomes small as the writing/erasing are repeated.
As described above, it is difficult to thin the tunnel insulating film due to the problem in reliability of the tunnel insulating film which is specific to the non-volatile memory. Therefore, the floating gate type NAND flash memory is miniaturized by strain scaling in which the lateral direction is only shrunk. This makes apparent the problem due to the inter-cell interference effect.
Meanwhile, since the local trap type has less inter-cell interference in terms of its structure, and a leak phenomenon of the tunnel insulating film is limited to the local trap concerning a leak path generated in the tunnel insulating film, it is also superior in leak resistance (refer to SONY CX-PAL Vol. 52, Device having traveled in space, Low-cost embedded non-volatile memory device technology “MONOS”, for example).
In these respects, the local trap type memory cell has been expected as a favorable memory cell after the end of the miniaturization of the floating gate type memory cell.
The local trap type has the advantage that the energy of a tunnel electron is low and the charge trap is not likely to be generated in the insulating film because the tunnel insulating film is thin as compared with the floating gate type.
However, as the writing/erasing are repeated, the charge trap is generated in the tunnel insulating film in the local trap type also similar to the floating gate type. This trap causes the problem in reliability of the tunnel insulating film naturally.
In addition, further miniaturization in the local trap type causes an essential defect in which the number of the local traps in the charge accumulation layer is decreased and the charge amount which can be stored is also decreased. Thus, even when a very small amount of charge is removed from the local trap of the charge accumulation layer in the miniaturized memory cell, this considerably affects the threshold value of the memory cell.
For example, when it is assumed that a trap density of the charge accumulation layer is 1×1012 cm−2, the trap number of the charge accumulation layer is only four when a control gate has a planar size of 20 nm×20 nm. When only one trap among them is connected to the leak path, it means that 25% of the total charges are lost.
Such variation in the number of local traps makes the operation of the memory cell unstable.
Consequently, under the circumstances in which the number of the local traps in the charge accumulation layer (electron retention number) is decreased, and the threshold swing between the write state and the erase state of the memory cell becomes small, when the variation in the local trap number is taken into consideration, the threshold window cannot be secured and becomes extremely narrow and as a result, the read operation cannot be performed.
Under such circumstances, a next-generation memory such as a quantum dot memory has been proposed.
There are two prominent kinds of technologies.
One technology regards many varied quantum dots as one group considering that it is difficult to control the position of the single quantum dot and maintain the quality thereof.
For example, quantum dots are embedded in the tunnel insulating film to improve the writing characteristic. This technology is disclosed in R. Ohba, N. Sugiyama, J. Koga, and S. Fujita, “Silicon nitride memory with double tunnel junction”, 2003 Symposium on VLST Technology Dig. Tech. Paper, for example. In addition, the quantum dot itself can be used instead of the local trap.
According to these technologies, although the conventional memory cell characteristic can be partially improved, the floating gate itself cannot be miniaturized to the level that shows a quantum dot property, and essential progress cannot be expected, since the quantum dots are embedded in one floating gate. Furthermore, since the reliability of the tunnel insulating film containing the quantum dot layer is lower than the reliability of the floating gate type tunnel insulating film because of the quantum dots, its production cost is also increased.
The other is a technology using the quantum dot as the floating gate.
Based on a vertical structure in which a regular tetrahedral trench is formed in a GaAs substrate, a floating gate of 10 nm is formed in a self-aligned manner in a valley part of the trench without any positional variation (refer to M. Shima, Y. Sakuma, T. Futatsugi, Y. Awano, and N. Yokoyama, “Tetrahedral shaped recess channel HEMT with a floating quantum dot gate,” IEDM Tech. Dig., pp. 437-440, December 1998, for example).
For example, since data is stored by the presence of one electron, terabit-class scaling can be performed. However, since the size of the opening part of the trench is several microns actually, a cell area is considerably larger than that of the file memory using the silicon substrate.
That is, the key to the miniaturization of the cell lies in the miniaturization of the opening part. However, the miniaturization of the opening part of the trench is limited by the limitation of a thinned GaAs substrate because the source and drain are vertically arranged. In addition, since the GaAs substrate increases bit cost, it is not suitable for the file memory originally.
Meanwhile, many proposals have been already made for a memory principle using the quantum dots or silicon nano-dots (refer to Jpn. Pat. Appln. KOKAI Publication Nos. 2003-243615, 2004-241781, 2005-175224, 2005-252266, 2006-140482, 2006-269660, and 2006-32970, k. Nishiguchi, H. Inokawa, Y. Ono, A. Fujiwara, and Y. Takahashi, “Multilevel memory using an electrically formed single-electron box”, APPLIED PHYSICS LETTERS, VOLUME 85, NUMBER 7, pp. 1277-1270, 16 Aug., 2004, and T. Goto et al., “Molecular-Mediated Single-Electron Devices Operating at Room Temperature”, Japanese Journal of Applied Physics, Vol. 45, No, 5A, 2006, pp. 4285-4289, for example).
However, since these are proposed consistently for the memory principle, various problems have to be solved to complete the memory as the flash memory such as the NAND flash memory.
One of the above problems includes a memory cell array architecture.
Only after completing the memory cell array architecture, the amount of the charges (electrons or holes) stored in the floating gate can be controlled in unit of one or more, and a next generation multi-level memory in which two or more bits of data can be stored in one memory cell, that is, a random writable multi-dot flash memory that solves the problems in miniaturization and reliability can be established.
Thus, with the silicon technology, the new memory cell array architecture is expected to be developed in which the problem in reliability is solved by providing the gate insulating film and the tunnel insulating film separately, the floating gate can operate in the size showing the quantum dot behavior, and the random writing is possible.
A control technique of writing/erasing using a new memory cell array architecture of a multi-dot flash memory as a next generation-file memory is also important. Concretely speaking, a low power consumption of writing/erasing is fundamental to realize a next generation-file memory.